Graphics processing device with integrated programmable synchronization signal generation

ABSTRACT

An integrated graphics processor provides a type of universal programmable synchronization signal generation that provides a plurality of different formats of display synchronization signals. In one embodiment, the integrated graphics processor includes a graphic and video blender that mixes image layers together prior to output for display. The graphics and video blender receives graphics and video data obtained from a frame buffer that may contain multiple formats of data, such as data in different color spaces, such as in a YUV color space (i.e., as per ITU-R BT709 or ITU-R BT 601), and in RGB color space. The integrated graphics processor also includes an integrated (internal or on-chip) programmable embedded synchronization signal generator operatively coupled to the graphic and video blender, to provide a plurality of different formats of display synchronization signals for blended information based on a type of display device. Accordingly, the integrated graphics processor can be programmed to provide suitable luma and chroma display information for different types of display devices, such as standard television displays, HDTV displays, and other displays that may require, for example, embedded synchronization signals, an embedded multilevel synchronization signal, or a separate synchronization signal.

FIELD OF THE INVENTION

The invention relates generally to video graphics processing and moreparticularly to integrated graphics processors that provide analogoutput in different color space formats and that provide embeddedsynchronization signals for display devices.

BACKGROUND OF THE INVENTION

Computers or other display generating devices are known to include acentral processing unit, system memory, peripheral ports, audioprocessing circuitry, and video processing circuitry. Typically, thevideo processing circuitry receives graphics data from the centralprocessing unit and prepares it for display on a computer monitor,television, and/or LCD panel. The computer generates the graphics databy performing one or more applications such as word processingapplications, drawing applications, presentation applications, spreadsheets, operating system functionality, etc. The video graphicsprocessing circuit processes the graphics data to produce RGB (red,green, blue) digital data, which may be converted to analog data that isprovided to the monitor.

The video graphics circuitry may also include a video decoder and videocapture module for processing YUV data. The video decoder is operablycoupled to receive video signals from a video source such as a cablebox, satellite receiver, antenna, VCR, DVD player, etc. Upon receivingthe video signal, which is formatted for a television or other videodisplay device, the video decoder produces digital representationsthereof The digital representations are stored as YUV data (as usedherein, YUV includes YCbCr and YPbPr) in the video capture module. Forthe video graphics processor to process the YUV data, it first convertsthe YUV data into an RGB color base. Once in the RGB color base, thevideo graphics processor can blend the video data and graphics data toproduce an output image. Also YUV source data is not required sincegraphics processors can generate YPbPr from an image with just graphicsand no video.

The output image is in a digital RGB color base format and can beprovided directly to an LCD panel or converted to an analog RGB signalvia a digital-to-analog converter (DAC). If the computer is alsoproviding the output image to a television monitor, the digital RGBcolor base data is converted to YUV color base data. As such, the videographics processing circuitry would further include an RGB-to-YUVconverter.

As known in the art, high definition television standards define atrilevel embedded synchronization signal to provide horizontal, verticaland blanking synchronization for three wire component video analog YPbPror RGB based display devices. Other devices may require analog RGB dataand separate synchronization signals or separate wires resulting in afour or five wire system.

High definition television devices and high quality standard definitiontelevision, typically use an analog YPbPr (or RGB) three wire componentvideo input wherein the synchronization signals are embedded with theluma and chroma information, as known in the art. These are known ascomponent input televisions. A problem arises when a single integratedgraphics processor chip needs to send display information in multipleformats for different types of display devices, such as a componentinput television, versus a computer monitor, since conventionalintegrated graphics processors do not provide programmable embeddedsynchronization signal generation for output to different types ofdisplay devices, or the logic to convert from RGB to the component videoYPbPr color space.

One type of digital to analog converter (DAC) chip includes HDTVcompliant triple digital to analog converters which receive digitalinformation from a source and can output a trilevel synchronizationpulse along with the YPbPr information while also being programmable tooutput conventional analog RGB information. However, such integratedcircuits typically require additional external analog to digitalconversion circuitry and other circuitry to provide suitable input tothe digital to analog converter (DAC). Also, such digital to analogconverters cannot provide graphic and video blending or color spaceconversion (e.g., between RGB and YUV color space).

Accordingly, there exists a need for an improved integrated graphicsprocessor that provides integrated programmable synchronization pulsegeneration to provide different formats of display synchronizationsignals for blended information based on requirements of differentdisplay device types. It would be desirable if such a processor reducedoutput pin requirements compared to using external YPbPr encoders.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be more readily understood with reference to thefollowing drawings wherein:

FIG. 1 is block diagram illustrating one example of an integratedgraphics processor in accordance with one embodiment of the invention;and

FIG. 2 illustrates an integrated graphics processor in accordance withanother embodiment of the invention.

FIG. 3 is a block diagram illustrating one example of a programmableembedded synchronization signal generator in accordance with oneembodiment of the invention.

FIG. 4 is a diagram illustrating a tri-level synchronization pulse.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

Generally, an integrated graphics processor provides a type of universalprogrammable synchronization signal generation that provides a pluralityof different formats of display synchronization signals. In oneembodiment, the integrated graphics processor includes a graphic andvideo blender that mixes image layers together prior to output fordisplay. The graphics and video blender receives graphics and video dataobtained from a frame buffer that may contain multiple formats of data,such as data in different color spaces, such as in a YUV color space(i.e., as per ITU-R BT709 or ITU-R BT 601), and in RGB color space. Theintegrated graphics processor also includes an integrated (internal oron-chip) programmable embedded synchronization signal generatoroperatively coupled to the graphic and video blender, to provide aplurality of different formats of display synchronization signals forblended information based on a type of display device. Accordingly, theintegrated graphics processor can be programmed to provide suitable lumaand chroma display information for different types of display devices,such as standard television displays, HDTV displays, and other displaysthat may require, for example, embedded synchronization signals, anembedded multilevel synchronization signal, or a separatesynchronization signal.

In one embodiment, a separate programmable color conversion scalingpipeline is provided for graphics RGB information, and a separateprogrammable color conversion and scaling circuit is provided in anotherpipeline for video Y, Cb, Cr information. Both pipelines provide signedYPbPr/RGB/YCbCr information that is provided to a graphic and videoblender. An offset circuit provides suitable offset to generate unsignedYPbPr/RGB/YCbCr information to an integrated programmablesynchronization signal generator prior to being sent through a DAC foroutput.

FIG. 1 illustrates an integrated graphics processor 100 having agraphics and video blender 102, a programmable color converter, signalscaler and offset generator 104, a programmable synchronization signalgenerator 106, a multiplexer 107 and a digital to analog converter (DAC)108. The programmable color converter, signal amplitude scaler andoffset generator 104 includes one or more general purpose programmablematrix multipliers wherein each of the three component outputs is a sumof products of each of the component inputs (e.g., R, G and B) and aconstant offset term. The offset is used when the system utilizes dataemploying an embedded synchronization signal. As known in the art, theoffset provides a suitable DC offset such that the black level will bemore positive. For 8-bit YCbCr, 16 will be added to the Y and 128 addedto the Cb and Cr. This puts the black level at Y=16, Cb=128 and Cr=128.Similarly, for an analog YPbPr or RGB output, an offset will be added toeach component. The value of which would be sufficient to ensure the DACwould provide a positive voltage level for the negative embeddedsynchronization signal. Integrated graphics processor 100 may be anintegrated circuit integrated as a single package.

The integrated graphics processor 100 may be operatively coupled througha bus 109 to an on-chip or external frame buffer 111. For example, theframe buffer 111 may be integrated as part of the integrated graphicsprocessor 100 on a single chip. Alternatively, the integrated graphicsprocessor 100 may be a separate chip and external to the frame buffer111 if the frame buffer is in a separate integrated circuit package(s).The frame buffer 111 contains multiple formats of data for display on atleast one display device. For example, the frame buffer 111 includes RGBinformation such as graphics information, and may also contain videoinformation in a different format, such as YCbCr format. The integratedgraphics processor 100 is operatively coupled to the frame buffer 111and provides an embedded synchronization signal with data obtained fromthe frame buffer 111 for display on a plurality of display devicesrequiring different information formats. The processor device 100 alsooptionally provides separate synchronization signals 105, such as HSYNCand VSYNC signals and other related signals, if required by the attacheddisplay device, through CRT controller 103 and multiplexer 107.

An input video signal 110 received from any suitable video source, suchas a DVD player, television input, the frame buffer 111 or any othersuitable video source, is converted from one color space format toanother by converter 112. In this example, the input video signal 110may be in a YCbCr format and converter 112 converts it into an RGBoutput format 114. The blender 102 receives graphics information 116from a suitable graphic source, such as from a host processor or anyother source in, for example, a digital RGB format. Other information118 may also be input to the blender 102.

The blender 102 is a conventional graphics and video blender having aninput operative to receive the graphics 116 or video information 114. Inthis example, the video and graphics information 110 and 116 areobtained from the frame buffer 111 containing multiple formats of datafor display on a display device. The graphics and video blender 102 hasan output that outputs blended graphic and video information 120. Forexample, the blender 102, as known in the art, may be any suitablegraphic and video blender that provides suitable graphic and videooverlays, which mixes image layers together. The blended outputinformation 120 is output in an RGB format, since the blender blends theinformation in a common format. The blended output information 120 maybe communicated in a TMDS format or an LVDS format for display on a flatpanel or other suitable display devices. The blended output information120 may be output by multiplexer 107 to the DAC 108 or output in analogRGB format directly.

Alternatively, the blended output information 120 may be passed throughthe programmable color converter, signal scaler and offset generator 104and the integrated programmable synchronization signal generator 106.The programmable color converter signal scaler and offset generator 104is programmable through a set of register(s) 128 that contains suitablebits representing color space conversion definition data 124, signalscaling parameters 126 and offset parameters 122. However, anon-register based control may also be used. With a general purposematrix result, the set of registers 128 may be combined or may beseparate if desired. The offset generator generates a value of offsetbased on the blank level required for the embedded synchronizationsignal generator. The offset is set such that “black” data values inoutput information 120 map to the “blank” values in 132, to raise theblack level of each color component. It will be recognized that anysuitable offset generator may also be used. The programmable colorconverter signal scaler and offset generator 104 outputs an outputsignal 130 which has undergone color conversion, for example, from anRGB format to a digital YPbPr format, signal scaling, and offset, or anyone of these operations. The output signal 130 serves as input to theprogrammable embedded synchronization signal generator 106. The output130 does not include synchronization information but includes digitalluma and chroma information.

When generating YPbPr or RGB signals for a television, video informationalready has the proper nominal signal range and color saturation.However, graphics information typically has a wider nominal range andmore saturated color data that is best viewed on a television typedisplay (it is meant for a computer CRT). One way to resolve this isapplying color space conversion with different scaler factors to videoinformation and graphics information.

The programmable color converter 104 provides color conversion, forexample, based on sets of well known equations. For example, sincegraphics information typically has saturated color, lower ranges of RGBvalues are only necessary. However, video information typically has lesssaturated color and allows a higher range of RGB values. One algorithmmay be used when the blended information 120 is graphics, and anotheralgorithm may be used if the blended information is video. However, thesame conversion algorithm may be used of all data if desired. Oneexample of color conversion performed by the programmable colorconverter, signal scaler and offset generator may be as follows.However, it will be recognized that any suitable conversion method mayalso be used. For conversion, a single programmable matrix multipliermay be used. The blender 102 applies a flag bit indicating whether theinformation on bus 120 is originally graphics information or videoinformation. For example, if multiplexed blending is used, a flag bit toindicate whether the data is graphics or video is generated based onwhether the surface that each pixel came from is graphics or video. Theflag bit is used by the programmable color converter 104 to select theappropriate coefficients as shown in the following equations for videoinformation:

Y=0.299R+0.587G+0.114B

Cb=−0.169r−0.331G+0.500B+128

Cr=0.500R−0.419G−0.081B+128

For graphics data, coefficients are selected as shown in the followingconversion equations:

Y=0.257R+0.504G+0.098B+16

Cb=−0.148R−0.291G+0.439B+128

Cr=0.439R−0.368G−0.071B+128

A programmable signal scaler operates to effectively scale input signalsto the DAC to a level acceptable by the DAC so that the input signals tothe DAC fit into the output range of the DAC. By way of example, if RGBdata 120 ranging from 0-255 is output by blender 102, and the DAC 108 isa 10 bit DAC, the YPbPr can range from 0-1023 for each. Therefore, lumadata is scaled and chroma data is scaled accordingly. Assuming thedigital YPbPr 130 has a “blank” level at 300, values 0-299 are for syncsignals only (below the blank level) and values 300-1023 can be used forvisible display data. Therefore, chroma offsets (Coffset) and lumaoffsets (Loffset) are used where the embedded synchronization formatrequires signals below the “blank” level. If the embeddedsynchronization format does not require signals below the “blank”, nooffsets are necessary.

The programmable color converter, signal scaler and offset generator 104may include a separate circuit or circuits for each of the operations.For example, the programmable color converter may include a color spaceconverter circuit or algorithm which is operatively coupled to thegraphic and video blender that includes a plurality of programmablematrix multipliers that perform color conversion from one color space toanother color space. Accordingly, the color space converter isoperatively coupled to the graphic and video blender 102 and providesconversion of graphic data or video data from a first format to a secondformat.

The programmable color converter, signal scaler and offset generator 104may operate according to the following matrix equations and may performthe calculations in essentially one step:

For color conversion of video information pixels to 10 bit YCbCr:$\begin{bmatrix}Y^{\prime} \\{Cb}^{\prime} \\{Cr}^{\prime}\end{bmatrix} = {{\begin{bmatrix}0.299 & 0.587 & 0.114 \\{- 0.169} & {- 0.331} & 0.500 \\0.500 & {- 0.419} & {- 0.081}\end{bmatrix}*\begin{bmatrix}R \\G \\B\end{bmatrix}} + \begin{bmatrix}0 \\{512} \\{512}\end{bmatrix}}$

For the case where a 10 bit DAC white level (input=1023) is 1.100V andthe desired Y blank level is 286 mV and desired Y nominal white level is1.000V then use the Y′ to Y conversion equation:

VoltScale=1100 mV/1023 steps=1.075 mV/step

YScale=((NominalWhiteVolt−BlankVolt)/VoltScale)/(NominalWhiteLevel−BlankLevel)=((1000mV−286 mV)/1.075 mV/step)/(940 step−64 step)=0.758

YOffset=BlankVolt/VoltScale−BlankLevel*YScale=286 mV/1.075 mV/step−64step*0.758=217.5

Y=YScale*Y′+YOffset=0.758*Y′+217.5

And for the same DAC with a 1023 input level mapping to 1.100V output,the Cb′Cr′ to PbPr mapping for the case where the PbPr zero point is tobe at 500 mV with a +/−350 mV nominal range the conversion is asfollows:

PScale=(PNominalRangeVolt/VoltScale)/(ChromaNominalTopLimit−ChromaNominalBottomLimit)=(2*350mV/1.075 mV/step)/(960 step−64 step)=0.7266

POffset=(PzeroVolt/VoltScale)−ChromaZero*PScale=(500 mV/1.075mV/step)−512*0.7266=93

Pb=PScale*Cb′+POffset=0.7266*Cb′+93

Pr=PScale*Cr′+POffset=0.7266*Cr′+93

When the above are multiplied together, the following mapping directlyfrom RGB to YPbPr is obtained and may be performed in one step:$\begin{bmatrix}Y \\{Pb} \\\Pr\end{bmatrix} = {{\begin{bmatrix}0.194 & 0.381 & 0.074 \\{- 0.107} & {- 0.211} & 0.318 \\0.318 & {- 0.266} & {- 0.052}\end{bmatrix}*\begin{bmatrix}R \\G \\B\end{bmatrix}} + \begin{bmatrix}266 \\465 \\465\end{bmatrix}}$

One of ordinary skill in the art will recognize that the resultingequations can be readily determined if the DAC nominal white level isdifferent than 1.100V, or if different Y nominal blank and white levelsare desired, or if different PbPr scaling and offsetting is desired fora specific YPbPr standard. In particular, any DC offset value could beused in any of the Y, Pb or Pr outputs by adjusting these equationswithout affecting the results as long as the output signals still havethe required scales and sync ranges needed for the television input.

The integrated programmable embedded synchronization signal generator106 is operatively coupled to the digital YPbPr 130 to receivesynchronization signals 105 (e.g., horizontal and verticalsynchronization signals), to provide a plurality of different formats ofdisplay synchronization signals 132 for blended information based on atype of display device receiving output signals from the DAC 108. Theprogrammable embedded synchronization signal generator 106 isprogrammable to output at least synchronization signals for componentvideo signals used in high definition television display devices and inhigh quality standard definition television display devices. Forexample, the programmable synchronization generator 106 is programmablethrough synchronization control register 134 to output at least anembedded synchronization signal, and a multilevel synchronizationsignal, such as a trilevel synchronization signal, or a negative syncpulse. A separate synchronization signal, such as sync signal 105, thatis not embedded with video information (e.g., luma and chromainformation) is provided by the CRT controller 103 and output throughmultiplexer 107. In addition, the programmable embedded synchronizationsignal generator 106 is programmable to provide variable synchronizationsignal slew rates and amplitudes. Sync signal 105 is generated when theblended output information 120 bypasses the programmable color converter104 and is passed to the multiplexer 107. The multiplexer 107 may be anysuitable multiplexer which is selectively controlled to select whetherto output digital YPbPr signal information 132 or the RGB information136 based on the type of display device.

The digital to analog converter 108 is operatively coupled to theprogrammable embedded synchronization signal generator 106 and outputsanalog signals including processed video or graphics data and at leastan embedded synchronization signal as output 132 for output to a displaydevice.

Where the programmable embedded synchronization signal generator 106generates a trilevel embedded synchronization signal for HDTV's, thetrilevel embedded synchronization signal may be of the type defined inCEA 770.3. The programmable embedded synchronization signal generator106 can also be programmed to generate negative sync signals such asthose defined in CEA 770.1 and 770.2.

Accordingly, the integrated graphics processor 100 contains in oneembodiment on a single chip, a blender 102, a programmable colorconverter, signal scaler and offset generator 104 and a programmableembedded synchronization signal generator 106 to provide programmabilityfor a graphics control chip to drive and provide suitable outputcompatible with different output standards.

FIG. 2 illustrates another embodiment of an integrated graphicsprocessor 200 for an HDTV set top box or other suitable application. Inthis embodiment, graphics information 116 and video information 110 arepassed through separate pipelines which include a programmable colorconverter and signal scaler 202 a and 202 b. Each of the programmablecolor converter and signal scalers 202 a and 202 b may be of the sametype described with respect to the programmable color converter, signalscaler and offset generator 104 of FIG. 1. However, the offset generatorhas been removed to a new point in FIG. 2. The programmable colorconverter and signal scaler 202 a and 202 b output signed YPbPr, signedRGB, or signed YCbCr data indicated at 204 a and 204 b. Blender 206suitably mixes layers and blends the graphics and video information 204a and 204 b and outputs a signed blended output 208 to an offsetgenerator 210. The offset generator 210 offsets the signed output YPbPror signed RGB or signed YCbCr information similar to the offsetgenerator of the programmable color converter signal scaler and offsetgenerator 104 as described above. The offset generator 210 by offsettingeach of the luma and chroma components, outputs blended unsignedinformation 212 to the programmable embedded synchronization signalgenerator 106. In this embodiment, the programmable embeddedsynchronization signal generator 106 outputs the embeddedsynchronization signal information 132 as described above. In thisembodiment, the blending is performed after color conversion signalscaling. It will also be recognized that other variations may also bedesirable.

In this embodiment, the color conversion is done on signed data.However, where YUV and YCbCr are unsigned, each are converted to asigned value by subtracting its offset. This is the purpose of theConstant (Const) below. A scaling algorithm is used to scale down thedata such that the resultant data will be in the range of the DAC, suchas the type of scaling algorithm described above. The function of thecolor converter is to implement a 4×3 matrix that is performed by matrixmultiplication using a programmable matrix multiplier that is suitableprogrammed with the matrix values as required. As with the aboveembodiment, the programmable matrix multipliers are programmable toapply a different transformation to convert pixels from a first colorformat to a second color format. A color conversion matrix as shownbelow may be used. $\begin{bmatrix}{YG} \\{PbB} \\{PrR}\end{bmatrix} = {{\begin{bmatrix}{C00} & {C01} & {C02} \\{C10} & {C11} & {C12} \\{C20} & {C21} & {C22}\end{bmatrix}\begin{bmatrix}{YG} \\{CbB} \\{CrR}\end{bmatrix}} + \begin{bmatrix}{Const0} \\{Const1} \\{Const2}\end{bmatrix}}$

Where YG=Luma or green data, CbB/PbB=Cb or Pb or Blue data, CrR/PrR=Cror Pr or Red data, C<num>=signed floating point coefficient,Const<num>=signed floating point coefficient.

For example, suppose we wanted to convert from RGB to YCbCr 601 usingthe equations below. $\begin{bmatrix}G \\B \\R\end{bmatrix} = {\begin{bmatrix}1.000 & {- 0.3441} & {- 0.7141} \\1.000 & 1.7720 & 0.0000 \\1.000 & 0.0000 & 1.4020\end{bmatrix}\begin{bmatrix}Y \\{Cb} \\{Cr}\end{bmatrix}}$

In order to do any type of manipulation to the data, we must convert theunsigned values to a signed value (i.e., remove the DC offset). For an8-bit YCbCr 601, there is a DC offset of 16 on the Y and 128 on the Cband Cr for 8-bit video. Therefore, the matrix becomes $\begin{bmatrix}G \\B \\R\end{bmatrix} = {\begin{bmatrix}1.000 & {- 0.3441} & {- 0.7141} \\1.000 & 1.7720 & 0.0000 \\1.000 & 0.0000 & 1.4020\end{bmatrix}\begin{bmatrix}{Y - 16} \\{{Cb} - 128} \\{{Cr} - 128}\end{bmatrix}}$ ${\text{or}\begin{bmatrix}G \\B \\R\end{bmatrix}} = {{\begin{bmatrix}1.000 & {- 0.3441} & {- 0.7141} \\1.000 & 1.7720 & 0.0000 \\1.000 & 0.0000 & 1.4020\end{bmatrix}\begin{bmatrix}Y \\{Cb} \\{Cr}\end{bmatrix}} + {{\begin{bmatrix}1.000 & {- 0.3441} & {- 0.7141} \\1.000 & 1.7720 & 0.0000 \\1.000 & 0.0000 & 1.4020\end{bmatrix}\begin{bmatrix}{- 16} \\{- 128} \\{- 128}\end{bmatrix}}}}$

which becomes $\begin{bmatrix}G \\B \\R\end{bmatrix} = {{\begin{bmatrix}1.000 & {- 0.3441} & {- 0.7141} \\1.000 & 1.7720 & 0.0000 \\1.000 & 0.0000 & 1.4020\end{bmatrix}\begin{bmatrix}Y \\{Cb} \\{Cr}\end{bmatrix}} + \begin{bmatrix}119 \\243 \\195\end{bmatrix}}$

Again using the scale from the previous example, Yscale=0.758 the datais scaled to the DAC level. So the final equation becomes.$\begin{bmatrix}G \\B \\R\end{bmatrix} = {{\begin{bmatrix}0.758 & {- 0.2608} & {- 0.5413} \\0.758 & 1.3432 & 0.0000 \\0.758 & 0.0000 & 1.0627\end{bmatrix}\begin{bmatrix}Y \\{Cb} \\{Cr}\end{bmatrix}} + \begin{bmatrix}90 \\184 \\147\end{bmatrix}}$

Once the matrix calculation is performed, by both color converters to acommon format, they are blended using the blender 208. The offsetgenerator 210 adds a constant value (Ie. Yoffset) to the blender resultsobtained above and the result 212 is clamped so the values do not exceeda predetermined limit.

FIG. 3 illustrates one example of the programmable embeddedsynchronization signal generator 106. FIG. 4 graphically illustrates atri-level synchronization pulse and a broad pulse that can be generatedby the programmable embedded synchronization signal generator. The broadpulse is only on lines containing VSYNC as known in the art. Theprogrammable embedded synchronization signal generator 106 includes asynchronization signal generator for Y or G 300, a synchronizationsignal generator 302 for Pb, Pr, B or R, a first multiplexer 304, asecond multiplexer 306, and a third multiplexer 308. The operation ofthe embedded synchronization signal generators 300 and 302 will bedescribed also with reference to FIG. 4. Where the synchronizationcontrol register data 310 indicates that the synchronization generator300 is to generate an embedded synchronization signal, a positive YGtri-level synchronization signal may be embedded by determining if eachsynchronization start portion of the input signal is equal to HCOUNT,where HCOUNT is a horizontal counter that spans the width of thedisplay. If so, the process includes starting at the YG blank level andadding a YG synchronization increment until a YG positivesynchronization level is reached. The synchronization generator 300 willcount horizontal clocks (e.g. HCOUNT values) until this synchronizationwidth is reached. Once reached, the synchronization generator 300 willsubtract a YG synchronization increment until the YG blank level isreached.

For the synchronization generator 300 to generate a negative YGtri-level embedded synchronization signal, the synchronization generator300 determines if an early horizontal sync start signal portion is equalto an HCOUNT value as provided by the CRTC. If so, the synchronizationgenerator 300 starts at a YG blank level and subtracts YGsynchronization increments until a YG negative sync level is reached.The synchronization generator 300 then counts horizontal clocks untilthe synchronization width is reached. Once reached, the synchronizationgenerator 300 adds the YG synchronization element until the YG blanklevel is reached. The CRTC controls the select signal 312 to output theappropriate embedded synchronization information and data as required,to the DAC.

To provide an embedded YG broad pulse, the synchronization generator 300determines if the broad pulse start signal portion is equal to HCOUNTand is in a vertical synchronization region. If so, the synchronizationgenerator 300 starts at the YG blank level and subtracts the YGsynchronization increment until the YG negative synchronization level isreached. The synchronization generator 300 then counts the horizontalclocks until a broad pulse width is reached. Once reached, thesynchronization generator 300 adds YG synchronization increments untilthe blank level is reached. As used herein, the YG synchronizationsignal can be equal to a positive YG tri-level synchronization signal, anegative YG tri-level synchronization signal, or a YG broad pulsesynchronization signal. synchronization signal, a negative YG tri-levelsynchronization signal, or a YG broad pulse synchronization signal.

The synchronization generator 302 likewise generates positive andnegative tri-level synchronization signals and broad pulsesynchronization signals. To generate a positive PbPr and BR tri-levelsynchronization signal, the synchronization generator 302 determines ifthe HSYNC start equals the HCOUNT. If so, the synchronization generator302 starts at the Pb, Pr or BR (blue or red) blank level and adds a Pb,Pr or BR synchronization increment until a Pb,Pr positivesynchronization level is reached. The synchronization generator 302 thencounts horizontal clocks until a synchronization width is reached. Oncereached, the synchronization generator 302 subtracts the PbPrsynchronization increment until the PbPr blank level is reached.

The synchronization generator 302 generates a negative Pb, Pr tri-levelembedded synchronization signal by determining if an early HSYNC startequals the HCOUNT value. The synchronization generator 302 starts at thePb, Pr blank level and subtracts the Pb, Pr synchronization incrementuntil the Pb, Pr negative synchronization level is reached. Thesynchronization generator then counts the horizontal clocks until asynchronization width is reached. Once reached, the synchronizationgenerator 302 adds the Pb, Pr synchronization increment until the Pb, Prlevel is reached.

To generate a Pb, Pr broad pulse, the synchronization generator 302determines if the broad pulse start has begun by comparing it to anHCOUNT value and if the broad pulse start occurs in a VSYNC region. Ifso, the synchronization generator 302 starts at the Pb, Pr blank leveland subtracts the Pb, Pr synchronization increment until the Pb, Prnegative synchronization level is reached. The synchronization generator302 then counts the horizontal clocks until a broad pulse width isreached. Once reached, the synchronization generator adds the Pb, Prsynchronization increment until a Pb, Pr blank level is reached. Thesynchronization generators 300 and 302 may be implemented using anysuitable logic, or may be implemented in software, if desired.

The data multiplexer 304 is controlled by the CRTC through select line312 such that if received data is not in a vertical blank or horizontalblank region, the multiplexer 304 is controlled to output Y or G data.Otherwise, it is controlled to output the Y or G synchronization pulse314.

The Pb, Pr multiplexers 306 and 308 are controlled by the CRTC throughselect line 312 such that if the received signal is not in a verticalblank or horizontal blank region, the multiplexers are controlled tooutput Pb, Pr data. Otherwise, the multiplexers 308 and 306 arecontrolled to output the Pb, Pr or BR synchronization signal 316 asembedded synchronization information. The sync control register 134 andCRTC are used to control the sync generators and multiplexers tooptionally turn on or off the negative and/or positive sync portion ofthe tri-level sync signal and broad pulse to provide outputs such asthose defined by CEA 770.1, 770.2, 770.3 or any suitable standard orrequirement.

It should be understood that the implementation of other variations andmodifications of the invention in its various aspects will be apparentto those of ordinary skill in the art, and that the invention is notlimited by the specific embodiments described. It is thereforecontemplated to cover by the present invention, any and allmodifications, variations, or equivalents that fall within the spiritand scope of the basic underlying principles disclosed and claimedherein.

What is claimed is:
 1. An integrated graphics processor comprising: agraphic and video blender having an input operative to receive graphicsor video data obtained from a frame buffer containing multiple formatsof data for display on at least one display device, and an having anoutput; and a programmable embedded synchronization signal generatoroperatively coupled to the output to provide a plurality of differentformats of display synchronization signals for blended information basedon a type of the at least one display device.
 2. The integrated graphicsprocessor of claim 1 including a digital to analog converter (DAC)operatively coupled to the programmable embedded synchronization signalgenerator that outputs analog signals including processed video orgraphics data and at least one of a programmed display synchronizationsignal.
 3. The integrated graphics processor of claim 1 wherein theprogrammable embedded synchronization signal generator is programmableto output at least component video synchronization signals for a highdefinition television display device and for a high quality standarddefinition television display device.
 4. The integrated graphicsprocessor of claim 1 wherein the programmable embedded synchronizationsignal generator is programmable to output at least one of the followingformats: an embedded synchronization signal, a multi-levelsynchronization signal and a separate synchronization signal.
 5. Theintegrated graphics processor of claim 1 wherein the programmableembedded synchronization signal generator is programmable to providevariable synchronization signal slew rates and amplitudes.
 6. Theintegrated graphics processor of claim 1 wherein the frame buffer ison-chip with the graphics processor.
 7. The integrated graphicsprocessor of claim 1 wherein the frame buffer is external to theintegrated graphics processor.
 8. The integrated graphics processor ofclaim 1 including a programmable offset circuit operatively coupled tothe programmable embedded synchronization signal generator to generate avalue of offset based on the blank level required for the programmableembedded synchronization signal generator.
 9. The integrated graphicsprocessor of claim 1 including a color space converter operativelycoupled to the graphic and video blender.
 10. The integrated graphicsprocessor of claim 9 wherein the color space converter includes aplurality of programmable matrix multipliers wherein each matrixmultiplier is programmable to apply a different transformation toconvert pixels from a first color format to a second color format. 11.The integrated graphics processor of claim 2 wherein the DAC outputs RGBinformation with embedded synchronization information.
 12. An integratedgraphics processor comprising: a graphic and video blender having aninput operative to receive graphics or video data obtained from a framebuffer containing multiple formats of data for display on at least onedisplay device, and an having an output; a programmable embeddedsynchronization signal generator operatively coupled to the output toprovide a plurality of different formats of display synchronizationsignals for blended information based on a type of the at least onedisplay device; a color space converter operatively coupled to thegraphic and video blender to provide conversion of graphics data orvideo data from a first format to a second format; and a digital toanalog converter (DAC) operatively coupled to the programmable embeddedsynchronization signal generator that outputs analog signals includingprocessed video or graphics data and at least one of a programmeddisplay synchronization signal.
 13. The integrated graphics processor ofclaim 12 wherein the programmable embedded synchronization signalgenerator is programmable to output at least component videosynchronization signals for a high definition television display deviceand for a high quality standard definition television display device.14. The integrated graphics processor of claim 13 wherein theprogrammable embedded synchronization signal generator is programmableto output at least one of the following formats: an embeddedsynchronization signal, a multi-level synchronization signal and aseparate synchronization signal.
 15. The integrated graphics processorof claim 14 wherein the programmable embedded synchronization signalgenerator is programmable to provide variable synchronization signalslew rates and amplitudes.
 16. The integrated graphics processor ofclaim 12 wherein frame buffer is on-chip with the graphics processor.17. The integrated graphics processor of claim 12 wherein frame bufferis external to the integrated graphics processor.
 18. The integratedgraphics processor of claim 12 including a programmable offset circuitoperatively coupled to the programmable embedded synchronization signalgenerator to generate a value of offset based on the blank levelrequired for the programmable embedded synchronization signal generator.19. The integrated graphics processor of claim 12 wherein the colorspace converter includes a plurality of programmable matrix multiplierswherein each matrix multiplier is programmable to apply a differenttransformation to convert pixels from a first color format to a secondcolor format.
 20. The integrated graphics processor of claim 13 whereinthe DAC outputs RGB information with embedded synchronizationinformation.
 21. A graphics processing system comprising: a frame bufferoperative to contain multiple formats of data for display on at leastone display device; and an integrated graphics processor operativelycoupled to the frame buffer having a programmable embeddedsynchronization signal generator operatively coupled to provide anembedded synchronization signal for use by a display device.
 22. Thegraphics processing system of claim 21 wherein the integrated graphicsprocessor includes: a graphic and video blender having an inputoperative to receive graphics or video obtained data from the frame andan having an output; and a programmable embedded synchronization signalgenerator operatively coupled to the output to provide a plurality ofdifferent formats of display synchronization signals for blendedinformation based on a type of the display device.
 23. The graphicsprocessing system of claim 21 including a digital to analog converter(DAC) operatively coupled to the programmable embedded synchronizationsignal generator that outputs analog signals including processed videoor graphics data and at least one of a programmed displaysynchronization signal.
 24. The graphics processing system of claim 22wherein the programmable embedded synchronization signal generator isprogrammable to output at least component video synchronization signalsfor a high definition television display device and for a high qualitystandard television display device.
 25. The graphics processing systemof claim 22 wherein the programmable embedded synchronization signalgenerator is programmable to output at least one of the followingformats: an embedded synchronization signal, a multi-levelsynchronization signal and a separate synchronization signal.
 26. Thegraphics processing system of claim 22 wherein the programmable embeddedsynchronization signal generator is programmable to provide variablesynchronization signal slew rates and amplitudes.
 27. The graphicsprocessing system of claim 21 wherein the frame buffer is on-chipintegrated in with the integrated graphics processor.
 28. The graphicsprocessing system of claim 21 wherein the frame buffer is external tothe integrated graphics processor.
 29. The graphics processing system ofclaim 21 wherein the integrated graphics processor includes aprogrammable offset circuit operatively coupled to the programmableembedded synchronization signal generator to provide an offsetcorresponding to a sign of a YPbPr value.
 30. The graphics processingsystem of claim 21 wherein the integrated graphics processor includes acolor space converter operatively coupled to the graphic and videoblender.
 31. The graphics processing system of claim 30 wherein thecolor space converter includes a plurality of programmable matrixmultipliers wherein each matrix multiplier is programmable to apply adifferent transformation to convert pixels from a first color format toa second color format.